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Silicon Labs /Series0 /EZR32HG /EZR32HG320F64R67 /USART0 /STATUS

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Interpret as STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXENS)RXENS 0 (TXENS)TXENS 0 (MASTER)MASTER 0 (RXBLOCK)RXBLOCK 0 (TXTRI)TXTRI 0 (TXC)TXC 0 (TXBL)TXBL 0 (RXDATAV)RXDATAV 0 (RXFULL)RXFULL 0 (TXBDRIGHT)TXBDRIGHT 0 (TXBSRIGHT)TXBSRIGHT 0 (RXDATAVRIGHT)RXDATAVRIGHT 0 (RXFULLRIGHT)RXFULLRIGHT

Description

USART Status Register

Fields

RXENS

Receiver Enable Status
TXENS

Transmitter Enable Status
MASTER

SPI Master Mode
RXBLOCK

Block Incoming Data
TXTRI

Transmitter Tristated
TXC

TX Complete
TXBL

TX Buffer Level
RXDATAV

RX Data Valid
RXFULL

RX FIFO Full
TXBDRIGHT

TX Buffer Expects Double Right Data
TXBSRIGHT

TX Buffer Expects Single Right Data
RXDATAVRIGHT

RX Data Right
RXFULLRIGHT

RX Full of Right Data

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data